Many different types and styles of semiconductor memory devices exist to store data for electronic devices such as computers, portable media players, and digital cameras. For example, dynamic random access memory and static random access memory are two types of volatile memory. Programmable read only memory, electrically erasable programmable read only memory (EEPROM), and flash memory are three common types of nonvolatile memory. Unlike many types of other electronic devices, such as capacitors, resistors, and many field-effect transistors, memory cells of flash and EEPROM nonvolatile memory have a relatively short life span. In other words, the memory cells can only be erased and have values stored in them a finite number of times, or cycles, before becoming unreliable. Although the expected life spans vary according to memory types, physical constructions, methods of writing and erasing, the life span of many nonvolatile memory varies between ten thousand and one hundred thousand erase/write cycles.
Some devices employ a technique called wear leveling. Wear leveling helps extend the life span of a nonvolatile memory devices by manipulating data in such a manner that erases and re-writes of the data are distributed or shared over the entire memory device. By moving data saves around the device, no single cell or particular group of cells fail prematurely due to repetitive erasures and re-writes of data. Consequently, the overall life span of the memory device may be considerably increased.
Unfortunately, current wear leveling techniques have several deficiencies. First, the wear leveling mechanisms for memory devices are inapplicable to devices that employ direct memory access. For example, the wear leveling mechanisms for flash memory are not applicable to memory-mapped devices. Several issues arise due to the fact that wear leveling techniques are applied at the flash translation layer (FTL). Unfortunately, when a platform boots it accesses the flash memory through direct-mapped low-level driver accesses which do not employ wear leveling mechanisms. Second, many wear leveling mechanisms today employ complex algorithms that significantly impact performance of the devices accessing the memory. These inherent delays tend to become more pronounced and noticeable as the flash memories increase in size.